1. Field of the Invention
The present invention relates to a decoder circuit, and more particularly, to a predecoder circuit positioned between an address decoder circuit and another decoder circuit in a semiconductor memory device.
2. Description of the Related Art
In recent years, a semiconductor memory device, which performs a high-rate operation, has played a large role in rapidly enhancing the performance of a personal computer and a workstation.
The semiconductor memory device includes an address decoder circuit, a predecoder circuit, and a decoder circuit, and these circuits select a word line as described later.
One example of a conventional predecoder circuit will be described with reference to FIG. 14. FIG. 14 shows an example in which three addresses are inputted, and this predecoder circuit includes first to third P channel (Pch) transistors P1 to P3 and first to third N channel (Nch) transistors N1 to N3.
Input signals A, B, and C are applied as address signals. When the potential levels of the address signals A, B, and C are "high levels (H)", the first to third Nch transistors N1 to N3 are placed in an ON state, and the first to third Pch transistors P1 to P3 are placed in an OFF state. As a result, the charge of a node X is discharged to GND. Moreover, the potential of an output /OUT has a low level (L). That is, the output /OUT is in a selection state.
When at least one of the address signals A, B, and C has a "L" level, at least one of the first to third Nch transistors N1 to N3 is in the OFF state, so that the path between the node X and GND is interrupted. On the other hand, when at least one of the first to third Pch transistors P1 to P3 is in the ON state, the node X is charged with an electric charge from a power supply Vcc, and becomes the "H" level. The output/OUT becomes "H" level, that is, a non-selection state.
Another example of the conventional predecoder circuit will next be described with reference to FIG. 15. The depicted predecoder circuit uses a Pch transistor P1 whose gate electrode connects to GND. Therefore, the Pch transistor P1 is normally on. The predecoder circuit is provided with the address signals A, B, and C in a similar manner as the predecoder circuit shown in FIG. 14. As described with reference to FIG. 14, when the potentials of the address signals A, B, and C are "H", the first to third Nch transistors N1 to N3 are in the ON state. As a result, the charge supplied to the node X via the Pch transistor P1 is discharged to GND. The potential of the node X results in "L" level, and the output/OUT results in the "L" level, that is, the selection state.
On the other hand, when at least one of the address signals A, B, and C is the "L" level, at least one of the first to third Nch transistors N1 to N3 is placed in the OFF state, so that the path between the node X and GND is interrupted. The potential of the node X results in "H" level by the charge supplied to the node X via the normally on Pch transistor P1. Subsequently, the output /OUT assumes the "H" level, that is, the non-selection state.
Another example of a conventional predecoder circuit will now be described with reference to FIG. 16. The depicted predecoder circuit uses a source drive system. When the potentials of the address signals A and B become "H", the first and second Nch transistors N1 and N2 are placed in the ON state. On the other hand, an address signal /C which is an opposite-phase signal of the address signal C is inputted to the source of the second Nch transistor N2 at the "L" level. The potential of the node X results in "L". Subsequently, the output /OUT results in the "L" level, that is, the selection state.
When at least one of the address signals A and B is the "L" level, the path between the second Nch transistor N2 and the node X is interrupted. Then, the potential of the node X results in "H" by the charge supplied to the node X via the normally-on Pch transistor P1. Subsequently, the output /OUT assumes the "H" level, which is the non-selection state.
Additionally, when the first and second Nch transistors N1 and N2 are in the ON state, and the potential of the address signal /C is "H", the node X results in the "H" level by the "H" level of the address signal /C and the charge supplied to the node X via the normally-on Pch transistor P1. The output /OUT results in the non-selection state of the "H" level.
In the predecoder circuits shown in FIGS. 14, 15 and 16, in order to adjust the switching speed from selection state to non-selection state and back again, the gate width ratio of the Pch/Nch transistors is changed. However, when the gate width of the Nch transistor is enlarged, or the gate width of the Pch transistor is reduced, in order to increase the switching speed from the non-selection state to the selection state, conversely, the switching speed from the selected state to the non-selected state is decreased, and undesired multi-selection may occur. Therefore, the predecoder circuits shown in FIGS. 14, 15 and 16 have a problem that it is difficult to increase the selection speed.
Furthermore, in the predecoder circuit shown in FIG. 16, a signal line with a large capacity load is used as a source input in order to increase the speed. In the predecoder circuit shown in FIG. 16, however, since amplification is fully performed in an output stage, the charge has to be discharged to the GND level from the Vcc level during selection, thereby slowing down the selection speed. This also applies to the predecoder circuit shown in FIGS. 14 and 15.
In the above-described predecoder circuit, since the P/N ratio is constant in accordance with a dimension during the switch to the selection state from the non-selection state, it is difficult to increase the selection speed without delaying the switching from the selection state to the non-selection state.